This invention relates to digital phase comparators as may be used in phase locked loops, and more particularly to phase comparators with improved sensitivity for detecting small differences in phase between input signals.
Phase locked loops (PLL) are used in diverse applications including frequency synthesizers, phase modulators, FM modulators, FM demodulators, radio frequency communication equipment, and controllers for variable speed electric motors.
The controlled variable in a PLL is phase. The phase of a first signal is compared to the phase of a second signal. The phase difference between the first and second signals is used in a feedback control system to bring the first and second signals into fixed phase relationship.
In a typical PLL, the first signal, a reference signal of reference frequency f.sub.r, and the second signal, a controlled signal of variable frequency f.sub.v, are compared by a digital phase comparator, which provides output indication proportional to phase error. The digital phase comparator has two outputs. One output (U) provides output pulses when the phase of the controlled signal is lagging with respect to the phase of the reference signal. When active, the duration of the U output pulses is proportional to the amount of phase lag. Conversely, the other output (D) provides output pulses when the phase of the controlled signal is leading with respect to the phase of the reference signal and, when active, the duration of the D output pulses is proportional to the amount of phase lead.
In a PLL, the U and D output signals from the phase detector are converted to ternary logic form and applied to an integrator to increase or decrease, respectively, the level of an output control voltage. In particular, the U output pulses operate a first charge pump to source current to a circuit node. The D output pulses operate a second charge pump to sink current from the same circuit node. The net current at such circuit node is integrated over time by a capacitor connected to the node to provide an output control voltage proportional to the time integral of detected phase error.
In the system just described, the phase comparator, the two charge pumps, and the integrator, comprise the phase correction portion of a PLL. The output of the phase correction means in turn operates a voltage controlled oscillator (VCO), the output of which is the controlled signal f.sub.v. A phase error exists between the reference signal and the controlled signal until the PLL adjusts the frequency of the controlled signal to be substantially equal to the frequency of the reference signal.
In the prior art, phase correction means in PLL's are incapable of detecting small differences in phase between the reference signal and the control signal. Thus a "dead zone" exists between phase lead and phase lag in which the loop phase correction means is insensitive to small phase errors. The dead zone is generally undesirable because, as the loop frequently drifts, the loop feedback mechanism cannot correct for the drift until the phase error becomes large enough to extend past the dead zone of the phase correction means. Therefore, the dead zone permits random frequency modulation as the loop frequency and phase wanders from one end of the dead zone to the other, which frequency modulation degrades the spectral purity of the PLL signal.
The overall PLL system dead zone results from several sources. The phase comparator may itself have a dead zone. That is, when the phase error is very small, neither U or D pulses may be produced. However, the major cause of the dead zone is attributed to the response of the charge pump to the U and D pulses. For example, even if the phase detector had ideal characteristics in the region about zero phase error, a dead zone would be created by the minimum turn on time of the charge pump alone. That is, when the phase error is very small, the U and D pulses may be so narrow as to have no appreciable effect on the charge pump output.
One prior art solution to the above described dead zone problem is to deliberately introduce leakage into the integrator means. This causes the integrator output to tend to droop with time, which droop is counterbalanced by the loop feedback. However, this technique is not desirable since it increases the amplitude of the sidebands at the reference frequency.
Another prior art solution to the above described problem is disclosed in U.S. Pat. No. 4,023,116 to Alfke, et al wherein a deliberate error pulse is injected on the D signal which produces a compensating phase error pulse from the phase comparator on the U signal. The phase comparator and phase correction means is thus effectively operated away from, or outside of, its dead zone. Such operation, however, produces a phase locked output signal having an undesirable phase error with respect to the reference frequency. Furthermore, introduction of error pulses into a PLL can adversely effect loop transient characteristics and increase system susceptibility to jitter.